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A Structured Visual Approach to GALS Modelling and Verification of Communication Circuits

Lookup NU author(s): Dr Frank Burns, Dr Danil Sokolov, Professor Alex Yakovlev



This is the authors' accepted manuscript of an article that has been published in its final definitive form by IEEE, 2017.

For re-use rights please refer to the publisher's terms and conditions.


In this paper a novel Globally Asynchronous Locally Synchronous (GALS) modelling and verification tool is introduced for xMAS circuits. The tool provides a structured environment for GALS in which organisation of the modelling and verification enables it to handle a variety of implementation tasks facilitating a process which would otherwise be difficult for the end user. The tool provides verification techniques at different levels. A new unfolding algorithm is presented that uses Structured Occurrence nets. A novel representation for deadlocks is introduced using deadlock relations enabling the causality of local and global deadlocks to be visualised. This helps in the investigation of total or partial system shutdown. In particular, the approach enables the visualisation of point-to-point causality of problems occurring between different parts of the system which are more difficult to analyse. In addition different types of deadlock related to the synchroniser can be detected. The work presented here provides structured visualisation capability facilitating the analysis of complex communication systems.

Publication metadata

Author(s): Burns F, Sokolov D, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2017

Volume: 36

Issue: 6

Pages: 938-951

Print publication date: 01/06/2017

Online publication date: 20/09/2016

Acceptance date: 23/08/2016

Date deposited: 30/09/2016

ISSN (print): 0278-0070

ISSN (electronic): 1937-4151

Publisher: IEEE


DOI: 10.1109/TCAD.2016.2611508

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