Power proportional adder design for Internet of Things in a 65nm process

Wheeldon, A; Morris, J; Sokolov, D; Yakovlev, A

doi:10.1109/PATMOS.2017.8106973

Power proportional adder design for Internet of Things in a 65nm process

Lookup NU author(s): Adrian Wheeldon ORCiD, Jordan Morris, Dr Danil Sokolov, Professor Alex Yakovlev

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This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2017.

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Abstract

In this paper we present a self-timed, power proportional, 32-bit ripple-carry adder design using a state-of-the art cell library. The cell library implements a new transistor sizing strategy for subthreshold in a commercial 65 nm low power process. Simulation results show improvements in performance and energy per cycle when compared to a fixed-period design. The adder has applications in the internet of things where systems are required to operate over a wide range of conditions and with varying power supplies.