Pulse controlled memristor-based delay element

Bunnam, T; Soltan, A; Sokolov, D; Yakovlev, A

doi:10.1109/PATMOS.2017.8106977

Pulse controlled memristor-based delay element

Lookup NU author(s): Dr Danil Sokolov, Professor Alex Yakovlev

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This is the authors' accepted manuscript of a conference proceedings (inc. abstract) that has been published in its final definitive form by IEEE, 2017.

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Abstract

Computing circuits suffer from the process, voltage and temperature variations and aging. These factors reduce yield and lifetime of the circuits and therefore limit the advance in modern computing technology. The process variations and aging result in timing failures that often can be resolved by delay matching. However, this strategy requires delay elements which cause additional power cost. We propose an alternative approach to implementing a pulse controlled delay element using a novel “memristor” device. The delay element has three modes of operation: tune up, tune down and normal. The main advantage of this approach is the energy efficiency due to the absence of the current path in the normal mode. Furthermore, as memristor is a non-volatile device, the proposed delay element does not need to be re-initialized every time the system starts. Thus, it can save startup power and time, which is also critical in the beyond CMOS computing. We also identify and propose a solution to the backward tuning problem which occurs when the amplitude of the normal signal is higher than the memristor threshold. A prototype was built based on ferroelectric parameter set with VTEAM model and the high voltage AMS 0.35μm technology. The simulation results showed an effective delay range from 5.48ns to 13.54ns in 6 steps with the minimum tuning pulse width of 3ns and the average delay of 1.34ns per step.