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Significance-Driven Logic Compression for Energy-Efficient Multiplier Design

Lookup NU author(s): Dr Issa Qiqieh, Dr Rishad Shafik, Dr Ghaith Tarawneh, Dr Danil Sokolov, Professor Alex Yakovlev



This is the of an article that has been published in its final definitive form by IEEE, 2018.

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Crown Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for an 128-bit multiplier, compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.0028 mean relative error. Additionally, we demonstrate the performance-energyquality (PEQ) trade-offs for different degrees of compression, achieved through configurable logic clustering. While evaluating the effectiveness of the proposed approach three case studies were set up. First, a Gaussian blur filter was designed, which demonstrated up to 80% energy reduction with a meagre loss of image quality. Second, we evaluate our approach in machine learning application using perceptron classifier, showed up to 74% energy reduction with negligible error rate. Third, the proposed multiplier designs were used in a power-constrained image processing application. We showed that SDLC can achieve 60x improvement in computation capability, with potential to be employed in ubiquitous systems.

Publication metadata

Author(s): Qiqieh I, Shafik R, Tarawneh G, Sokolov D, Das S, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Year: 2018

Volume: 8

Issue: 3

Pages: 417-430

Online publication date: 11/06/2018

Acceptance date: 08/06/2018

Date deposited: 26/06/2018

ISSN (print): 2156-3357

ISSN (electronic): 2156-3365

Publisher: IEEE


DOI: 10.1109/JETCAS.2018.2846410


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