Assessment method of dead-time compensation schemes of three-phase inverters using a hardware-in-the-loop configuration

Bojoi, R; Armando, E; Mariut, F; Odhano, S

doi:10.1109/ECCE.2015.7310238

Assessment method of dead-time compensation schemes of three-phase inverters using a hardware-in-the-loop configuration

Lookup NU author(s): Dr Shafiq Odhano ORCiD

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Abstract

© 2015 IEEE. This paper proposes a testing method for the evaluation of the inverter dead-time voltage error and the related compensation schemes using a hardware-in-the loop converter topology. The inverter under test is operated as a voltage source that is connected with another twin inverter acting as a virtual load. The virtual load is operated as a current-controlled voltage source converter that draws specified currents having a desired amplitude and phase displacement respect to the voltages generated by the inverter under test. The two converters share the same DC link, so the power required for the test must cover only the total converter losses. This testing approach allows a complete analysis and assessment of dead-time compensation schemes for any operating conditions, such as modulation index, current value and power factor.