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Burst Automaton: Framework for Speed-Independent Synthesis using Burst-Mode Specifications

Lookup NU author(s): Dr Alex Chan, Dr Danil Sokolov, Dr Victor Khomenko, Professor David Lloyd, Professor Alex Yakovlev



This is the authors' accepted manuscript of an article that has been published in its final definitive form by Institute of Electrical and Electronics Engineers, 2022.

For re-use rights please refer to the publisher's terms and conditions.


Burst-Mode (BM) formalism is a variant of an asynchronous Finite State Machine (FSM) that operates in ‘burst-mode’ timing assumption and offers simple entry into asynchronous circuit design.However, some of BM’s well-formedness properties, while useful for implementing BM specifications as circuits, are rather restrictive in some important contexts e.g. BM’s maximal set property (or its analog, Extended Burst-Mode (XBM) formalism’s distinguishability constraint) forbids non-deterministic specifications that are inherent in some design approaches, input and output bursts must alternate meaning BMs are not a proper extension of FSMs with arcs labelled by single events, and BMs cannot express input-output concurrency whereas FSMs can with interleaving. The latter limitation is particularly problematic when interoperability between several formalisms is desirable.In this paper, we propose the Burst Automation (BA) model that is more powerful and yet simpler than BM, by relaxing BM’s well-formedness properties. BA is a proper extension of FSMs, and can express input-output concurrency and non-determinism. We define BA’s interleaving semantics via its asynchronous reachability graph that is an FSM, and develop three translations from BAs to Signal Transition Graphs (STGs) that preserve strong bisimulation, weak bisimulation, or the language. Former two translations may be exponential, whereas latter translation is linear. The resulting STG can then be used for verification and synthesis into Speed-Independent (SI) or Quasi-Delay-Insensitive (QDI) circuits, or for composition with other STGs.The proposed workflow was implemented in WORKCRAFT, and experimental results show an improved synthesis rate and a significant reduction in the literal count.

Publication metadata

Author(s): Chan A, Sokolov D, Khomenko V, Lloyd D, Yakovlev A

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

Year: 2022

Volume: 42

Issue: 5

Pages: 1560-1573

Print publication date: 01/05/2023

Online publication date: 14/09/2022

Acceptance date: 06/09/2022

Date deposited: 29/09/2022

ISSN (print): 0278-0070

ISSN (electronic): 1937-4151

Publisher: Institute of Electrical and Electronics Engineers


DOI: 10.1109/TCAD.2022.3206732

ePrints DOI: 10.57711/3cj0-4488


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