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Lookup NU author(s): Dr Danil Sokolov, Dr Alex Bystrov, Professor Alex Yakovlev
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Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method. (16 References).
Author(s): Sokolov D, Murphy J, Bystrov A, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Cryptographic Hardware and Embedded Systems - CHES 2004
Year of Conference: 2004
Pages: 282-97
ISSN: 978-3-540-22666-6
Publisher: Springer
Notes: Joye M Quisquater J-J Berlin, Germany. Cryptographic Hardware and Embedded Systems - CHES 2004. 6th International Workshop. Proceedings. Cambridge, MA, USA. 11-13 Aug. 2004.
Library holdings: Search Newcastle University Library for this item
Series Title: Lecture Notes in Computer Science
ISBN: 3540226664
