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Lookup NU author(s): Dr Gordon Russell
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This paper describes a modification to the Brent & Kung (M-B&K) adder which not only increases the speed of operation but also reduces the amount of the hardware for its implementation. This modified adder is being incorporated into a 32-bit RISC processor which has a concurrent error detection capability. (3 References).
Author(s): Maanmar AH, Russell G
Publication type: Article
Publication status: Published
Journal: WSEAS Transactions on Circuits and Systems
Year: 2004
Volume: 3
Issue: 9
Pages: 2058-2061
ISSN (print): 1109-2734
Publisher: World Scientific and Engineering Academy and Society
Notes: Publisher: WSEAS, Greece.
