Browse by author
Lookup NU author(s): Professor Anthony O'Neill,
Dr Jun Zhang
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
The relative performance enhancement of strained-Si and buried channel p-MOS as a function of lithographic and effective gate lengths were investigated. Si- pMOS device results are presented from a standard 0.25 mu m CMOS process. A SiGe buried channel device on a SiGe virtual substrate is also investigated. With the different diffusion constants for Si and SiGe layers part of this enchancement may be related to differences in channel length. To remove any such effects, the effective gate length (L/sub eff/) was extracted using the shift and ratio technique and performance improvements have been compared for both lithographic gate length (L/sub g/) and effective gate length (L/sub eff/). (4 References).
Author(s): Temple MP, Paul DJ, Tang YT, Waite AM, Evans AGR, O'Neill AG, Zhang J, Grasby T, Parker EHC
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 2003 International Semiconductor Device Research Symposium
Year of Conference: 2003
Notes: Piscataway, NJ, USA.
2003 International Semiconductor Device Research Symposium. Washington, DC, USA. IEEE. Electron Device Soc. Nat. Sci. Found. Army Research Laboratory. Naval Research Laboratory. Army Research Office. Nat. Inst. of Standards and Technol. Elec. and Comput. Eng. Dept., Univ. of Maryland. 10-12 Dec. 2003.