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E-BIST: Enhanced test-per-clock BIST architecture

Lookup NU author(s): Dr Gordon Russell

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Abstract

A new built-in self-test architecture, E-BIST, suitable for a test-per-clock scheme, is proposed. The E-BIST architecture is based on STUMPS, which uses a linear feedback shift register (LFSR) as the test generator, a multiple input shift register (MISR) as the response compactor, and shift register latch (SRL) channels as multiple scan paths. In E-BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS technique. It is also shown that the masking probability of the proposed SRL channel structure is 21-(N+L), where N and L are the number of test patterns and the length of the SRL channel, respectively. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for robustly detecting path delay faults, with improved fault coverage, when the Hamming distance of the data in the SRL channel is considered.

Publication metadata

Author(s): Russell G; Son Y; Chong J

Publication type: Article

Publication status: Published

Journal: IEE Proceedings: Computers and Digital Techniques

Year: 2002

Volume: 149

Issue: 1

Pages: 9-15

ISSN (print): 1350-2387

ISSN (electronic): 1359-7027

Publisher: IEEE

URL: http://dx.doi.org/10.1049/ip-cdt:20020158

DOI: 10.1049/ip-cdt:20020158

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