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Optimisation of a 4H-SiC Enhancement Mode Power JFET

Lookup NU author(s): Dr Alton Horsfall, Dr Christopher Johnson, Professor Nick Wright, Professor Anthony O'Neill


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An optimised enhancement mode JFET structure determined by TCAD simulation is presented. The device has been simulated using Medici TCAD software for fabrication in 4H-SiC. Investigations of critical device parameters have been studied allowing for the proposed optimal structure. The forward current and forward blocking voltage are optimised simultaneously by examining the variation of the device switching power, defined in this context as the product of the forward blocking voltage and the forward current density, as a function of the channel width and trench depth. Channel width is shown to have the most dramatic effect on the device performance for this structure. The optimised structure has a blocking voltage of 650 V for zero bias gate voltage with a 250 A cm-2 forward current, at a gate voltage of 2.5 V.

Publication metadata

Author(s): Horsfall AB, Johnson CM, Wright NG, O'Neill AG

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 4th European Conference on Silicon Carbide and Related Materials (ECSCRM 2002)

Year of Conference: 2003

Pages: 777-780

ISSN: 9780878499205

Publisher: Trans Tech Publications

Library holdings: Search Newcastle University Library for this item

Series Title: Materials Science Forum

ISBN: 0878499202