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Lookup NU author(s): Peter Hyde, Dr Gordon Russell
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The use of deep sub-micron technology raises a number of concerns about reliability in VLSI circuits. Shrinking geometries and reduced power supplies leave the circuits vulnerable to 'soft' and transient errors. The combination of high clock speed and large circuit area result in high power consumption and skew in clock distribution. This paper investigates the use of Concurrent Error Detection (CED) and asynchronous design to overcome these problems. Four pipelined processor designs are compared - two synchronous, two asynchronous with one of each type using CED. Initial results indicate an area overhead of 12% in return for a fault coverage of 98.54% of all unidirectional errors. Additionally, the asynchronous CED processor has an area overhead of only 4% when compared to the synchronous non-CED design.
Author(s): Hyde PD, Russell G
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: 10th IEEE International On-Line Testing Symposium (IOLTS 2004)
Year of Conference: 2004
Pages: 89-94
Publisher: IEEE
URL: http://dx.doi.org/10.1109/OLT.2004.1319664
DOI: 10.1109/OLT.2004.1319664
Library holdings: Search Newcastle University Library for this item
ISBN: 0769521800
