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2D device-level simulation study of strained-Si pnp heterojunction bipolar transistors on virtual substrates

Lookup NU author(s): Dr Nebojsa Jankovic Professor, Professor Anthony O'Neill

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Abstract

A novel strained-Si pnp heterojunction bipolar transistor (HBT) design, suitable for virtual substrate technology, is proposed that is inherently free from the detrimental valence band barrier effects usually encountered in conventional SiGe pnp HBTs on silicon. It takes advantage of the heterojunction formed between a strained-Si layer and a relaxed SiGe buffer (virtual substrate), whose associated valence band offset appears favorable for minority hole transport at the base/collector junction. From two-dimensional (2D) numerical simulation, it is found that the newly proposed strained-Si pnp HBT substantially outperforms the equivalent BJT on a silicon substrate in terms of DC and high-frequency characteristics. A threefold increase in maximum current gain β, a fourfold improvement in peak ft and a 2.5 times increase in peak fmax are predicted for strained-Si pnp HBTs on a 50% Ge virtual substrate in comparison with identical conventional silicon pnp BJTs. © 2003 Elsevier Ltd. All rights reserved.


Publication metadata

Author(s): Jankovic ND, O'Neill A

Publication type: Article

Publication status: Published

Journal: Solid-State Electronics

Year: 2004

Volume: 48

Issue: 2

Pages: 225-230

ISSN (print): 0038-1101

ISSN (electronic): 1879-2405

Publisher: Pergamon

URL: http://dx.doi.org/10.1016/S0038-1101(03)00300-9

DOI: 10.1016/S0038-1101(03)00300-9


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