Browse by author
Lookup NU author(s): Henning Bahr, Dr Gordon Russell, Dr Yajian Li
Full text for this publication is not currently held within this repository. Alternative links are provided below where available.
We present a novel test architecture which combines IEEE 1149.1 Boundary-Scan with a Memory Built-In Self-Test. The TDI pin is used for serially shifting in the test data into a test data register which is connected to the memory. The finite state machine of the TAP controller performs the memory test algorithm. The test response is shifted out via the TDO pin for off-chip analyses. The test architecture offers small area over-head, acceptable test time, increased flexibility and analysis capabilities while maintaining compliance to the Boundary-Scan standard.
Author(s): Bahr H, Russell G, Li Y
Publication type: Article
Publication status: Published
Journal: WSEAS Transactions on Electronics
Year: 2005
Volume: 2
Issue: 4
Pages: 161-165
ISSN (print): 1109-9445
ISSN (electronic):
Publisher: World Scientific and Engineering Academy and Society
