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FPGA implementation of an asynchronous processor with both online and offline testing capabilities

Lookup NU author(s): Nikolaos Minas, Matthew Marshall, Dr Gordon Russell, Professor Alex Yakovlev



Due to aggressive technology scaling VLSI circuits have become more susceptible to transient errors. The associated reduction in supply voltages has decreased noise margins, causing system reliability to be reduced increasingly at a time when electronic systems are being used in "safety critical" applications. Clock distribution issues as well as the demands for low power circuits have exposed the limitations of the synchronous design paradigm. Asynchronous circuits appear to be an alternative, offering low power and low EMI. However the design complexity involved, the lack of CAD tools and the issues of testability have made this class of circuits unfavourable with digital designers. In this paper an asynchronous RISC based processor is introduced with both online and offline testing capabilities, thus offering a solution to the testability problem. The processor uses a Concurrent Error Detection (CED) scheme to identify transient errors. Detection of hard errors is done using an embedded asynchronous functional tester, where the asynchronous Device Under Test (DUT) is able to control the tester rather than being dictated by the clock in synchronous ATE. The processor and the equivalent test circuitry have been implemented on a Xilinx Virtex21000 FPGA. © 2008 IEEE.

Publication metadata

Author(s): Minas N, Marshall M, Russell G, Yakovlev A

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: 14th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2008)

Year of Conference: 2008

Pages: 128-137

Date deposited: 27/05/2010

Publisher: IEEE Computer Society


DOI: 10.1109/ASYNC.2008.13

Library holdings: Search Newcastle University Library for this item

ISBN: 9780769531076