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Lookup NU author(s): Santosh Shedabale, Dr Gordon Russell, Professor Alex Yakovlev
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in 'foundry' business where product volumes are low; consequently it is no longer feasible to optimise the process during the product lifetime resulting in an increase in parametric yield loss. This paper describes the use a combination of two statistical tools namely Design of Experiments (DoE) and Response Surface Modelling (RSM) which permit the identification and modelling of those process parameters whose variation which will impact most on the performance of a circuit. The efficiency of this approach, compared to using a Monte Carlo analysis, is demonstrated with respect to a Mutual Exclusion Element (MUTEX) which is used extensively in synchronisers where process variations can have considerable impact on circuit performance. To obtain the same modelling accuracy, the Monte Carlo approach would require large number of simulations compared to nine using the DoE scheme with the low computational overhead. This method can be used by semiconductor manufacturers and design house alike to bridge the gap between manufacture and design. © 2008 IEEE.
Author(s): Ramakrishnan H, Shedabale S, Russell G, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, ICICDT 2008
Year of Conference: 2008
Pages: 171-176
Date deposited: 25/05/2010
Publisher: IEEE
URL: http://dx.doi.org/10.1109/ICICDT.2008.4567272
DOI: 10.1109/ICICDT.2008.4567272
Library holdings: Search Newcastle University Library for this item
ISBN: 9781424418114
