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Improving the security of dual-rail circuits

Lookup NU author(s): Dr Danil Sokolov, Dr Julian Murphy, Dr Alex Bystrov, Professor Alex Yakovlev


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Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers: the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the transmitted data values. To generate these dual-rail circuits an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the Advanced Encryption Standard (AES) have been simulated and compared in order to evaluate the method.

Publication metadata

Author(s): Sokolov D, Murphy J, Bystrov A, Yakovlev A

Editor(s): Joye, M., Quisquater, J-J.

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Cryptographic Hardware and Embedded Systems (CHES): 6th International Workshop

Year of Conference: 2004

Pages: 282-297

ISSN: 0302-9743 (print) 1611-3349 (online)

Publisher: Springer


DOI: 10.1007/978-3-540-28632-5_21

Library holdings: Search Newcastle University Library for this item

Series Title: Lecture Notes in Computer Science

ISBN: 9783540226666