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Lookup NU author(s): Dr Delong Shang, Dr Frank Burns, Dr Alex Bystrov, Dr Albert Koelmans, Dr Danil Sokolov, Professor Alex Yakovlev
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The hardware implementation of AES algorithm as an asynchronous circuit has a reduced leakage of information through side-channels and enjoys high performance and low power. Dual-rail data encoding and return-to-spacer protocol are used to avoid hazards, including data-dependent glitches, and in order to make switching activity data-independent (constant). The implementation uses a coarse pipeline architecture which is different from traditional micropipelines. The pipeline stages are complex and have built-in controllers implemented as chains of David cells (special kind of latches), whose behaviour is similar to fine-grain pipelines. A highly balanced security latch is designed. The design is partly speed-independent; in a few places it uses well localised and justified relative timing assumptions. The security properties of the system are evaluated by extensive simulation and by counting switching activity.
Author(s): Shang D, Burns F, Bystrov A, Koelmans A, Sokolov D, Yakovlev A
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: Integrated Circuit and System Design
Year of Conference: 2004
Pages: 471-480
ISSN: 9783540230953
Publisher: Springer-Verlag Berlin and Heidelberg GmbH & Co. KG
Library holdings: Search Newcastle University Library for this item
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