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Lookup NU author(s): Dr Nick Bennett,
Professor Nick Cowern
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Simulation and physical experiments have shown that vacancy engineering implants have the potential to provide outstanding pMOS source/drain performance for several future CMOS device generations. Using vacancy-generating implants prior to boron implantation, hole concentrations approaching 10(21) cm(-3) can be achieved using low thermal budget annealing. In this new study we propose that the vacancy engineering technique is not reliant on the implementation of SOI-based CMOS but is also directly applicable to bulk silicon technologies.
Author(s): Bennett NS, Cowern NEB, Paul S, Lerch W, Kheyrandish H, Smith AJ, Gwilliam R, Seal BJ
Publication type: Conference Proceedings (inc. Abstract)
Publication status: Published
Conference Name: ESSDERC 2008: proceedings of the 38th European Solid-State Device Research Conference
Year of Conference: 2008
Publisher: Institute of Electrical and Electronics Engineers
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