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Lookup NU author(s): Santosh Shedabale,
Dr Gordon Russell,
Professor Alex Yakovlev,
Dr Sanatan Chattopadhyay
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The advances in semiconductor processing technologies have led to the need for a detailed understanding and stringent control of the variations in device performance. Statistical techniques provide methods, such as response surface modelling (RSM), to measure, characterise and model the variations, thus enabling an understanding and identification of the impact of these on both yield and performance of the devices and circuits built from advanced process technologies. The construction of response surface (RS) models, however, has been restricted to only a few variables, due to the number of TCAD simulations and hence the statistical analyses required for fitting sufficiently accurate models. The problem of modelling a large number of manufacturing process parameters is addressed by partitioning the parameters and subsequently building multi-level RS models which can analyse and predict the process variability. This approach greatly reduces (by approximately two to three orders of magnitude) the large number of TCAD simulations necessary to fit the RS models. The application of multi-level partitioned RSM is demonstrated on a 65 nm CMOS technology. With the device dimensions shrinking and the impact of manufacturing process variations becoming dominant on the device performance, the proposed approach plays a vital role in design for manufacturability. The variability information obtained from these models is important not only to control and optimise the process variation but also to quantify its effects on device and circuits designs.
Author(s): Shedabale S, Ramakrishnan H, Russell G, Yakovlev A, Chattopadhyay S
Publication type: Article
Publication status: Published
Journal: IET Circuits, Devices and Systems
ISSN (print): 1751-858X
ISSN (electronic): 1751-8598
Publisher: The Institution of Engineering and Technology
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