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Strained-Si n-MOS surface-channel and buried Si0.7Ge 0.3 compressively-strained p-MOS fabricated in a 0.25 μm heterostructure CMOS process

Lookup NU author(s): Dr Sarah Olsen, Professor Anthony O'Neill


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A 0.25 μm complimentary metal oxide semiconductor (CMOS) process has been used to fabricate surface channel strained-Si n-MOS devices and buried, compressively-strained-Si0.7Ge0.3 channel p-MOS. Enhancements in performance of on-current, transconductance and mobility over bulk, relaxed Si CMOS devices are demonstrated for both n- and p-MOS devices for all gate lengths fabricated from 0.1 up to 10 μm. The performance is compared to surface channel strained-Si CMOS which is superior to the buried channel results. Possible reasons are discussed. © 2004 Elsevier Ltd. All rights reserved.

Publication metadata

Author(s): Paul DJ, Temple M, Olsen SH, O'Neill AG, Tang YT, Waite AM, Cerrina C, Evans AGR, Li X, Zhang J, Norris DJ, Cullis AG

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Materials Science in Semiconductor Processing: 2nd International SiGe Technology and Device Meeting (ISTDM 2004)

Year of Conference: 2004

Pages: 343-346

ISSN: 1369-8001

Publisher: Pergamon


DOI: 10.1016/j.mssp.2004.09.106