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Lookup NU author(s): Layi Alatise, Dr Kelvin Kwa, Dr Sarah Olsen, Professor Anthony O'Neill
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The impact of the thickness of the silicon-germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 mu m strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 mu m thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 mu m SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 pm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes. (C) 2009 Elsevier Ltd. All rights reserved.
Author(s): Alatise OM, Kwa KSK, Olsen SH, O'Neill AG
Publication type: Article
Publication status: Published
Journal: Solid-State Electronics
Year: 2010
Volume: 54
Issue: 3
Pages: 327-335
ISSN (print): 0038-1101
ISSN (electronic): 1879-2405
Publisher: Pergamon
URL: http://dx.doi.org/10.1016/j.sse.2009.09.029
DOI: 10.1016/j.sse.2009.09.029
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