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Strained Si MOSFETs on relaxed SiGe platforms: Performance and challenges

Lookup NU author(s): Dr Sanatan Chattopadhyay, Dr Kelvin Kwa, Dr Sarah Olsen, Professor Anthony O'Neill

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Abstract

The purpose of this article is to briefly review the recent progress in terms of mobility and drive current enhancements achieved in strained-Si n- and p-metal oxide semiconductor field effect transistors (MOSFETs). Strained Si MOSFETs are potential candidates for future high performance CMOS applications, and the electron mobility enhancement factor over 3 and saturation drain current enhancement over 90% compared to bulk Si CMOS have been reported for surface channel device. The hole mobility enhancement factor over 2 has been achieved for the surface channel strained Si device while that for the buried channel compressively strained SiGe is reported to be over 5. Techniques for designing channel architectures of heterostructure CMOS (HCMOS) devices are discussed. The challenges in device design, thermal budget optimisation, SALICIDE issues and integration of different modules are addressed. © 2004 Published by Elsevier Ltd. All rights reserved.

Publication metadata

Author(s): Chattopadhyay S, Driscoll LD, Kwa KSK, Olsen SH, O'Neill AG

Publication type: Review

Publication status: Published

Journal: Solid-State Electronics

Year: 2004

Volume: 48

Issue: 8

Pages: 1407-1416

ISSN (print): 0038-1101

ISSN (electronic): 1879-2405

URL: http://dx.doi.org/10.1016/j.sse.2004.01.018

DOI: 10.1016/j.sse.2004.01.018

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