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Test chip for the development and evaluation of test structures for measuring stress in metal interconnect

Lookup NU author(s): Dr Alton Horsfall, Sorin Soare, Professor Nick Wright, Professor Anthony O'Neill, Professor Steve BullORCiD


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The development of a new test chip is presented, which contains the first test devices able to directly measure stress in metallic interconnect layers associated with silicon IC technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip has been used to fabricate working devices allowing the study of stresses in aluminium layers before and after sample sintering. The results are presented along with the design, fabrication and measurement considerations that have arisen during the research. Also discussed are the problems experienced with residual sacrificial layer material and the potential solutions that are under investigation. The sensor device is CMOS-compatible and its inherent scalability makes it suitable for in-line testing of state-of-the-art devices.

Publication metadata

Author(s): Terry JG, Smith S, Walton AJ, Gundlach AM, Stevenson JTM, Horsfall AB, Wang K, Dos Santos JMM, Soare SM, Wright NG, O'Neill AG, Bull SJ

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: IEEE International Conference on Microelectronic Test Structures

Year of Conference: 2004

Pages: 69-73


Publisher: Institute of Electrical and Electronics Engineers