Analysis of gate leakage in strained Si MOSFETs

Yan, L; Olsen, SH; Kanoun, M; Al-Araimi, M; Agaiby, R; Dalapati, GK; O'Neill, AG

doi:10.1149/1.2355894

Analysis of gate leakage in strained Si MOSFETs

Lookup NU author(s): Dr Sarah Olsen, Dr Mehdi Kanoun, Mohamed Al-Areeki, Rimoon Agaiby, Goutan Dalapati, Professor Anthony O'Neill

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Abstract

This work investigates gate leakage mechanisms in advanced strained Si/SiGe MOSFET devices. The impact of virtual substrate Ge content, epitaxial material quality, epitaxial layer structure and device processing on gate oxide leakage characteristics are analysed in detail. We show that at high oxide electric fields where gate leakage is dominated by F-N tunneling, tensile strained Si MOSFETs exhibit lower leakage levels compared with bulk Si devices. However for device operating regimes at lower oxide electric fields Poole-Frenkel (P-F) emissions contribute to strained Si gate leakage and increase with increasing virtual substrate Ge content. The emissions are shown to predominantly originate from surface roughness generating bulk oxide traps, opposed to Ge diffusion, and can be improved by introducing a high temperature anneal. Consequently advanced strained Si/SiGe devices are inadvertently subject to a potential trade-off between power consumption (gate leakage current) and device reliability (gate oxide interface quality). copyright The Electrochemical Society.