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Design, fabrication and characterisation of strained Si/SiGe MOS transistors

Lookup NU author(s): Dr Sarah Olsen, Dr Kelvin Kwa, Luke Driscoll, Dr Sanatan Chattopadhyay, Professor Anthony O'Neill


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Strained Si/SiGe heterostructure MOS transistors offer great promise for nanoscale CMOS/technology. This paper reviews these high performance devices and the challenges associated with their integration into conventional CMOS processes. Simulation results at a device and circuit level show that n-channel MOSFET performance can influence circuit speed to a greater extent than p-channel devices. Consequently the experimental work discussed is focused on recent progress in the optimisation of strained Si/SiGe n-channel MOSFETs. Simulation predicts that dual channel CMOS architectures offer the greatest performance advantages for both n- and p-channel MOSFETs. However, experimental evidence suggests that a single channel CMOS architecture may be a more pragmatic choice, given the material and processing complexities involved. The optimum SiGe alloy composition for virtual substrate based devices is discussed. Electron mobility is shown to peak in strained Si channels fabricated on relaxed Si0.75Ge0.25, yet wafer yield is compromised for virtual substrate compositions incorporating Ge contents above 15%. Optimum strained Si/SiGe device design is therefore shown to be highly dependent on the device parameter to be optimised, and specific processing conditions. © IEE, 2004.

Publication metadata

Author(s): Olsen SH, Kwa KSK, Driscoll LS, Chattopadhyay S, O'Neill AG

Publication type: Article

Publication status: Published

Journal: IEE Proceedings: Circuits, Devices and Systems

Year: 2004

Volume: 151

Issue: 5

Pages: 431-437

ISSN (print): 1350-2409

ISSN (electronic): 1751-8598

Publisher: The Institution of Engineering and Technology


DOI: 10.1049/ip-cds:20040995


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