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Doubling speed using strained Si/SiGe CMOS technology

Lookup NU author(s): Dr Sarah Olsen, Professor Anthony O'Neill, Dr Sanatan Chattopadhyay, Dr Kelvin Kwa, Luke Driscoll


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The benefit of high performance strained Si CMOS in terms of technology generations is quantified. It is shown that a 0.3 μm gate length strained Si/Si0.75Ge0.25 CMOS technology has the same gate delay as conventional technology having an effective gate length of 0.14 μm, but without the cost of re-tooling. Transconductance enhancements over conventional CMOS in excess of 200% are demonstrated for surface channel n- and p-MOSFETs using a Si0.75Ge0.25 virtual substrate without CMP and a high thermal budget process. To our knowledge these represent the best results reported to date at these dimensions. © 2005.

Publication metadata

Author(s): Olsen SH, Temple M, O'Neill AG, Paul DJ, Chattopadhyay S, Kwa KSK, Driscoll LS

Editor(s): S. Zaima, S. Miyazaki, S. Takagi, M. Miyao, J. Murota

Publication type: Conference Proceedings (inc. Abstract)

Publication status: Published

Conference Name: Fourth International Conference on Silicon Epitaxy and Heterostructures (ICSI-4)

Year of Conference: 2005

Pages: 338-341

ISSN: 0040-6090

Publisher: Thin Solid Films: Elsevier


DOI: 10.1016/j.tsf.2005.07.347