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Modeling of the threshold voltage in strained Si/Si1-x Gex/S1-yGey(x ≥ y) CMOS architectures

Lookup NU author(s): Dr Yuk Tsang, Dr Sanatan Chattopadhyay, Dr Suresh Uppal, Dr Enrique Escobedo-Cousin, Deepak Ramakrishnan, Dr Sarah Olsen, Professor Anthony O'Neill



In this paper, an analytical model of threshold voltage VT for globally strained Si/SiGe CMOS devices using a dualchannel architecture is proposed. Since band parameters modify VT, they are calculated and generalized for different Ge contents in a Si1-xGex film grown on relaxed Si1-y Gey virtual substrates (x, y > 0.7). A model for predicting VT is then developed by considering device geometry and material properties, including band parameters, permittivity, and channel and substrate doping concentrations. VT lowering due to short-channel effects is included by incorporating a voltage-doping transformation. Accuracy of the model is verified by comparing the model with the results of technology computer-aided design simulations and experiments. The model provides a physical insight for the variation of VT for both n- and p-MOSFETs in a dual-channel architecture, and it can be generalized to be applicable to single-channel devices as well. © 2007 IEEE.

Publication metadata

Author(s): Tsang YL, Chattopadhyay S, Uppal S, Escobedo-Cousin E, Ramakrishnan HK, Olsen SH, O'Neill AG

Publication type: Article

Publication status: Published

Journal: IEEE Transactions on Electron Devices

Year: 2007

Volume: 54

Issue: 11

Pages: 3040-3048

Print publication date: 01/11/2007

Date deposited: 26/05/2010

ISSN (print): 0018-9383

ISSN (electronic): 1557-9646

Publisher: IEEE


DOI: 10.1109/TED.2007.907190


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